Turning to FIG. 1 of the drawings, a timing diagram for a conventional SAR analog to digital converter (ADC) with a “convert and shut down” architecture can be seen. As can be seen, a conventional SAR ADC samples during the sample phase of the sample clock S (which has a period of operation TS) and converts during the convert phase of sample clock S. A amplifier, which is commonly used in the SAR ADC, is powered down during the sample phase and is powered up on the falling edge of the sample clock S. However, power-up of the amplifier or preamplifier requires time, TOC, which reduces the conversion period, TC. Thus, the speed or resolution of the SAR ADC is sacrificed for reduced power consumption.
Some examples of conventional devices are: European Patent No. 0559657; U.S. Pat. Nos. 5,138,319; 6,124,818; 6,879,277; 6,882,295; 6,882,298; 6,914,550; 6,950,052; 6,954,170; 6,956,520; 6,958,722; 6,977,607; 6,985,101; and PCT Publ. No. WO1992004777.